Leaked slide presented by Intel at the 2019 Intel Investor Meeting in Santa Clara
CHIPMAKER Intel’s Xeon CPU roadmap, providing the details of Intel’s next-generation server processors for the next three years, has been leaked online by WikiChip.
The roadmap runs into 2022 and provides a snapshot of the major features expected from Intel’s upcoming server microprocessors, and indicates that Intel plans to launch its 14nm Cooper Lake and 10nm Ice Lake-SP with PCIe Gen 4 in 2020.
Cooper Lake will be launched in two varieties – Cooper Lake SP (aimed at 2-way SMP) and Cooper Lake P (aimed at 4-way and 8-way SMP).
The 14nm Cooper Lake-SP family will be part of the Whitley Platform and is expected to feature up to 48 cores, 8 channel DDR4 memory as well as PCIe Gen 3 support. Cooper Lake P, on the other hand, may use of a “Cedar Island” platform in place of Whitley platform.
Intel 10nm+ Ice Lake-SP processors should be available from the second quarter of 2020. They will feature a maximum of 26 cores and eight-channel DDR4 memory. The most notable feature of these processors will be PCIe Gen 4 support, which will come to AMD’s upcoming second-generation Epyc microprocessors, codenamed Rome, in the third quarter this year.
The new Sunny Cove architecture, on which Ice Lake-SP processors will be based, is expected to provide instruction-per-cycle gains and an increase in overall efficiency.
In the first quarter of 2021, Intel plans to launch 10nm++ Sapphire Rapids-SP line-up, based on the updated Willow Cove core architecture. These processors will feature Octal-channel DDR5 memory and will also offer support for PCIe Gen 5 on the Eagle Stream platform.
Last week, Intel revealed the Sapphire Rapids codename for the first time and confirmed that Sapphire Rapids family will succeed both Ice Lake and Cooper Lake in the 2021 timeframe.
Intel is also expected to launch its first datacentre Xe GPUs based on the 7nm process node in 2021.
Later in 2022, the chipmaker will unveil 7nm Granite Rapids-SP along with Golden Cove chip core architecture. µ
Source : Inquirer